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87C196KT 87C196KS ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
( b 40 Ct a 125 C Ambient) o
Y Y Y Y
High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Register-Register Architecture 8 Channel 10-Bit A D with Sample Hold 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible Interfacing Oscillator Fail Detection Circuitry
Y
High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus (Programmable) Programmable Bus (HLD HLDA) 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide 68-Pin PLCC Package
Y
Y Y
Y Y Y Y Y Y Y
Y Y Y
Y Y Y Y
Y
Y
The 87C196Kx devices represents the 4th generation of MCS 96 microcontroller products implemented on Intel's advanced 1 micron process technology These products are based on the 80C196KB device with enhancements ideal for automotive applications The instruction set is a true super set of the 80C196KB with a few new instructions The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The 87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals Up to 32 Kbytes of Program EPROM up to 1 Kbytes of Register RAM (00-3FFH including SFRs) up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10 Bit g3LSB analog to digital converter with programmable S H times with conversion times k 20 ms at 16 MHz an asynchronous synchronous serial I O port (8096 compatable) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed I O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The PTS has several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode Additional SFR space is allocated for the EPA and can be ``windowed'' into the lower Register RAM area
NOTICE This datasheet contains information on products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1995 COPYRIGHT INTEL CORPORATION 1995
Order Number 270999-007
1
87C196KT 87C196KS
Device 87C196KT 87C196KS
Pins Package 68-Pin PLCC 68-Pin PLCC
EPROM 32K 24K
Reg RAM 1K 1K
Code RAM 512b 256b
IO 56 56
EPA 10 10
SIO Y Y
SSIO Y Y
AD 8 8
NOTE This is a PRODUCT PREVIEW DATA SHEET The AC and DC parameters contained within this data sheet may change after full automotive temperature characterization of the device has been performed Contact your local sales office before finalizing the Timing and D C characteristics of a design to verify you have the latest information
ARCHITECTURE
The KT KS are new members of the MCS-96 family having the same architecture and use the same instruction set as the 80C196KB Many new features have been added including
NEW INSTRUCTIONS
XCH XCHB Exchange the contents of two locations either Word or Byte is supported Interruptable Block Move Instruction allows the user to be interrupted during long executing Block Moves TIJMP Table Indirect JUMP This instruction incorportes a way to do complex CASE level branches through one instruction An example of such code savings several interrupt sources and only one interrupt vector The TIJMP instruction will sort through the sources and branch to the appropriate subcode level in one instruction This instruction was added especially for the EPA structure but has other code saving advantages EPTS DPTS Enable and Disable Interrupts (Works like EI and DI) BMOVI
CPU FEATURES
Y Y Y
Powerdown and Idle Modes 16 MHz Operating Frequency A High Performance Peripheral Transaction Server (PTS) 37 Interrupt Vectors Up to 512 Bytes of Additional Code RAM Up to 1 Kbyte of Additional Register RAM ``Windowing'' Allows 8-Bit Addressing to some 16-Bit Addresses 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide Oscillator Fail Detect Circuitry
Y Y
Y
Y
Y Y Y
SFR OPERATION
A total of 1 Kbyte of Register RAM is implemented on the 87C196KT KS devices These locations support the on-chip peripherals that the 87C196KT KS has (SFR's) as well as offering a data storage area These locations are all 8-bit directly addressable by use of the windowing technique Any 32- 64- or 128byte section can be relocated into the upper 32- 64or 128-byte area of the Register RAM area 080H - 0FFH
PERIPHERAL FEATURES
Programmable A D Conversion and S H Times 10 Capture Compare I O with 2 Flexible Timers (250 ns Resolution and Double Buffered Inputs) Synchronous Serial I O Port for Full Duplex Serial I O Synchronous Asynchronous Serial I O Port (with Dedicated 16-Bit Baud Rate Generator) Total Utilization of ALL Available Pins (I O Mux'd with Control) (2) 16-Bit Timers with Prescale Cascading and Quadrature Counting Capabilities Up to 12 Externally Triggered Interrupts
2
2
87C196KT 87C196KS
87C196KT Block Diagram
270999 - 1
270999 - 2
3
3
87C196KT 87C196KS
PIN DESCRIPTIONS
Symbol VCC VSS VSSI VSSI VREF Main supply voltage ( a 5V) Digital circuit ground (0V) There are three VSS pins all of which MUST be connected Reference for the A D converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Programming voltage for the EPROM parts It should be a 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC Reference ground for the A D converter Must be held at nominally the same potential as VSS Input of the oscillator inverter and the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency is has a 50% duty cycle Also LSIO pin the oscillator frequency It Name and Function
VPP
ANGND XTAL1 XTAL2 P2 7 CLKOUT RESET
Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared bytes are read from 2018H and 201AH loading the CCBs and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ``0'' and CCR1 bit 2 is ``1'' all bus cycles are 8-bit if CCR bit 1 is ``1'' and CCR1 bit 2 is ``0'' all bus cycles are 16-bit CCR bit 1 e ``0'' and CCR1 bit 2 e ``0'' is illegal Also an LSIO pin when not used as BUSWIDTH A positive transition causes a non maskable interrupt vector through memory location 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EPROM fetches INST is held low Also LSIO when not INST Input for memory select (External Access) EA equal to a high causes memory accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM ROM EA equal to a low causes accesses to these locations to be directed to off-chip memory EA e a 12 5V causes execution to begin in the Programming Mode EA is latched at reset Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not used as ALE Read signal output to external memory RD is active only during external memory reads or LSIO when not used as RD Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Also an LSIO pin when not used as WR WRL
P5 7 BUSWIDTH
NMI P5 1 INST
EA
P5 0 ALE ADV
P5 3 RD P5 2 WR WRL
4
4
87C196KT 87C196KS
PIN DESCRIPTIONS (Continued)
Symbol P5 5 BHE WRH Name and Function Byte High Enable or Write High output as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects that bank of memory that is connected to the low byte Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external memory write cycles Also an LSIO pin when not BHE WRH Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO pin when READY is not selected Dual function I O pin As a bidirectional port pin or as a system function The system function is a Slave Port Interrupt Output Pin Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Clock input The TIMER1 will increment or decrement on both positive and negative edges of this pin Dual function I O pin Primary function is that of a bidirectional I O pin however it may also be used as a TIMER1 Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low Dual function I O port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare EPA0 and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer counter 8-bit high impedance input-only port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins are also used as inputs to EPROM parts to select the Programming Mode Dual function I O ports that have a system function as Synchronous Serial I O Two pins are clocks and two pins are data providing full duplex capability 8-bit multi-functional port All of its pins are shared with other functions 8-bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups
P5 6 READY
P5 4 SLPINT P6 2 T1CLK
P6 3 T1DIR
PORT1 EPA0-7 P6 0-6 1 EPA8-9 PORT 0 ACH0-7
P6 3-6 7 SSIO PORT 2 PORT 3 and 4
5
5
87C196KT 87C196KS
CCB
0 1 2 3 4 5 6 7 PD
(2018H Byte)
e e e e e e e e
CCB1 (201AH Byte)
0 1 2 3 4 5 6 7 0 IRC2 BW1 WDE 1 0 MSEL0 MSEL1
e e e e e e e e
``1'' Enables Powerdown See Table ``1'' e WR BHE - ``0'' e WRL WRH ``1'' e ALE - ``0'' e ADV
Reserved Must Be ``0'' See Table See Table ``0'' e Always Enabled
BW0 WR ALE IRC0 IRC1 LOC0 LOC1
( See Table ( See Table
Function Read and Write Protected Write Protected Only Read Protected Only No Protection IRC2 0 1 1 1 1 BW1 0 0 1 1 0 1 0 1
( Reserved Must Be ``01'' ( See Table
Max Wait States Zero Wait States 1 Wait State 2 Wait States 3 Wait States INFINITE Bus Width ILLEGAL 16-Bit Only 8-Bit Only BW Pin Controlled
LOC1 0 0 1 1
LOC0
IRC1 0 0 0 1 1 BW0 0 1 0 1
IRC0 0 0 1 0 1
MSEL1 0 0 1 1
Mode 0 (1-Wait KR)
MSEL0 0 1 0 1
Bus Timing Mode Mode 0 (1-Wait KR) Mode 1 Mode 2 Mode 3 (KR)
Designed to be similar to the 87C196KR bus timing with 1 automatic wait state
See AC Timings section for actual timings data
Mode 1 RD WR advanced 1 TOSC ALE advanced 0 5 TOSC ALE pulse width remains 1 TOSC RD WR advanced 1 TOSC ALE advanced 0 5 TOSC ALE pulse width remains 1 TOSC Address advanced 0 5 TOSC Designed to be similar to the 87C196KR bus timing
Mode 2
Mode 3 (KR)
See AC Timings section for actual timings data
6
6
87C196KT 87C196KS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Voltage from VPP or EA to VSS or ANGND
b 60 C to a 150 C b 0 5V to a 13 0V
NOTICE This is a production data sheet The specifications are subject to change without notice
Voltage from Any Other Pin b 0 5 to a 7 0V to VSS or ANGND This includes VPP on ROM and CPU devices Power Dissipation 0 5W
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
OPERATING CONDITIONS
Symbol TA VCC VREF FOSC Parameter Ambient Temperature Under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min
b 40
Max
a 125
Units C V V MHz (Note 4)
4 50 4 50 4
5 50 5 50 16
NOTE ANGND and VSS should be nominally at the same potential
DC CHARACTERISTICS
Symbol ICC IREF IIDLE IPD VIL VIH VIH1 VIH2 Parameter
(Under Listed Operating Conditions)
Test Conditions XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V (While device in Reset) XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V(6 9) For PORT0(8) For PORT0(8) XTAL1 Input Pin Only(1) RESET input pin only
b 0 5V
Min
Typ
Max 82 5 40
Units mA mA mA mA V V V V
VCC Supply Current ( b 40 C to a 125 C Ambient) A D Reference Supply Current Idle Mode Current Powerdown Mode Current Input Low Voltage (all pins) Input High Voltage Input High Voltage XTAL1 Input High Voltage on RESET
50
TBD 0 3 VCC VCC a 0 5 VCC a 0 5 VCC a 0 5
0 7 VCC 0 7 VCC 0 7 VCC
7
7
87C196KT 87C196KS
DC CHARACTERISTICS
Symbol VOL
(Under Listed Operating Conditions) (Continued)
Test Conditions IOL e 200 mA(3 5) IOL e 3 2 mA IOL e 7 0 mA IOH e b 200 mA(3 5) IOH e b 3 2 mA IOH e b 7 0 mA VSS k VIN k VCC VSS k VIN k VREF IOH e 0 8 mA(7) IOH e b 15 mA(1 8) VOH2 e VCC b 1 0V VOH2 e VCC b 2 5V VOH2 e VCC b 4 0V ftest e 1 0 MHz(6) IOL3 e 4 mA(10) IOL3 e 6 mA IOL3 e 8 mA (Note 6) 65K 150K 180K 20 VCC b 1V
b 30 b 75 b 90 b 120 b 240 b 280
Parameter Output Low Voltage (Outputs Configured as Complementary) Output High Voltage (Outputs Configured as Complementary) Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) SLPINT (P5 4) and HLDA (P2 6) Output High Voltage in RESET Output High Voltage in RESET Output High Current in RESET
Min
Typ
Max 03 0 45 15
Units V V V V V V
VOH
VCC b 0 3 VCC b 0 7 VCC b 1 5
g10 g1 5
ILI ILI1 VOH1 VOH2 IOH2
mA mA V V mA mA mA pF V X X
CS VOL3
Pin Capacitance (Any pin to VSS) Output Low Voltage in RESET (RESET Pin Only) Weak Pullup Resistance Reset Pullup Resistor
10 03 05 08
RWPU RRST
NOTES 1 All BD (bidirectional) pins except INST and CLKOUT INST and CLKOUT are excluded due to their not being weakly pulled high in reset BD pins include Port1 Port2 Port3 Port4 Port5 and Port6 except SPLINT (P5 4) and HLDA (P2 6) 2 Standard input pins include XTAL1 EA RESET and Port 1 2 5 6 when setup as inputs 3 All bidirectional I O pins when configured as Outputs (Push Pull) 4 Device is static and should operate below 1 Hz but only tested down to 4 MHz 5 Maximum IOL IOH currents per pin will be characterized and published at a later date 6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5 0V 7 Violating these specifications in reset may cause the device to enter test modes (P5 4 and P2 6) 8 When P0 is used as analog inputs refer to A D specifications for this characteristic 9 For temperatures k100 C typical is 10 mA 10 This specification is not tested in production and is based upon theoretical estimates and or product characterization
ICC vs Frequency
270999 - 24
NOTES ICC Max e 3 25 c Freq a 30 IIDLE Max e 1 25 c Freq a 20
8
8
87C196KT 87C196KS
AC CHARACTERISTICS
(Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns The 87C196KT will meet these specifications Symbol FXTAL TOSC TXHCH TOFD TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low Clock Failure to Reset Pulled Low(6) CLKOUT Period CLKOUT High Period CLKOUT Low to ALE ADV High ALE ADV Low to CLKOUT High ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE INST Hold after WR High AD8-15 Hold after WR High BHE INST Hold after RD High AD8-15 Hold after RD High TOSC b 10
b 10 a 25
Min 40 62 5
a 20
Max 16 0 250 110 40 2 TOSC
Units MHz(1) ns ns ms ns ns ns ns ns(5) ns ns ns ns
4
TOSC b 10
b 10 b 25
TOSC a 30
a 15 a 15
4 TOSC TOSC b 10 TOSC b 15 TOSC b 40 TOSC b 40
b5 a 35
TOSC a 10
ns ns(5) ns(3) ns ns ns ns
TOSC b 5 TOSC TOSC a 25
a5
TOSC b 23
b 10 a 15
ns ns(5) ns ns(3) ns ns(4) ns ns(4)
TOSC b 30 TOSC b 30 TOSC b 10 TOSC b 10 TOSC b 30 TOSC b 10 TOSC b 30 TOSC a 15
NOTES 1 Testing performed at 4 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 Tosc c n where n e number of wait states If mode 0 (1 automatic wait state added) operation is selected add 2 TOSC to specification 6 TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H KT KS customer QROM codes need to equate location 2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired Intel manufacturing uses location 2016H as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit Programming the CDE bit enables oscillator fail detection
9
9
87C196KT 87C196KS
AC CHARACTERISTICS
(Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise anf Fall Times e 10 ns The system must meet these specifications to work with the 87C196KT Symbol TAVYV TLLYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 TOSC b 55 TOSC b 30 TOSC b 60 TOSC 0 Min Max 2 TOSC b 75 TOSC b 70 No Upper Limit TOSC b 30 2 TOSC b 75 TOSC b 60 Units ns(3) ns(3) ns ns(1) ns(2 3) ns(2 3) ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 Tosc c n where n e number of wait states 3 If mode 0 is selected one wait state minimum is always added If additional wait states are required add 2 Tosc to the specification
10
10
87C196KT 87C196KS
87C196KT SYSTEM BUS TIMING
270999 - 4
If mode 0 operation is selected add 2 Tosc to this time
11
11
87C196KT 87C196KS
87C196KT READY TIMINGS (ONE WAIT STATE)
270999 - 5
If mode 0 selected one wait state is always added If additional wait states are required add 2 Tosc to these specifications
87C196KT BUSWIDTH TIMINGS
270999 - 6
If mode 0 selected add 2 Tosc to these specifications
12
12
87C196KT 87C196KS
HOLD HOLDA TIMINGS
Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV
(Over Specified Operation Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns Parameter HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid
b 25 b 25 b 15 b 10 a 15
Min
a 65 b 15 b 15
Max
Units ns(1)
a 15 a 15 a 20 a 25 a 15 a 25
ns ns ns ns ns ns ns ns
NOTE 1 To guarantee recognition at next clock
8XC196KT HOLD HOLDA TIMINGS
270999 - 7
13
13
87C196KT 87C196KS
BUS MODE 1 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 87C196KT will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCHLH TCLLL TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHIX TWHAX TRHBX TRHAX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low CLKOUT Period CLKOUT High Period CLKOUT HIGH to ALE ADV High CLKOUT LOW to ALE ADV Low ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE Hold after WR High INST Hold after WR High AD8-15 Hold after WR High BHE Hold after RD High AD8-15 Hold after RD High AD8-15 Hold after RD High 0 5 TOSC b 10 TOSC b 15 2 TOSC b 23
b 10 a 15
Min 80 62 5
a 20
Max 16 0 125 110 2 TOSC
Units MHz(1) ns ns ns
TOSC b 10 0 5 TOSC b 15 0 5 TOSC b 25 TOSC b 10 0 5 TOSC b 15 0 5 TOSC b 20 0 5 TOSC b 30 TOSC b 10 2 TOSC b 20 0 5 TOSC
TOSC a 27 0 5 TOSC a 20 0 5 TOSC a 15 TOSC a 10
ns ns ns ns(5) ns ns ns ns
4 TOSC
TOSC a 30 0 5 TOSC a 25
a5
ns ns(5) ns(3) ns ns
TOSC a 25
ns ns ns ns(5) ns ns(3) ns ns(4) ns ns(4)
2 TOSC b 15 0 5 TOSC b 25 0 5 TOSC b 10 TOSC b 15 0 5 TOSC b 15 0 5 TOSC b 30 TOSC b 32 0 5 TOSC b 32 0 5 TOSC b 30 0 5 TOSC a 15
NOTES 1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 TOSC c n where n e number of wait states
14
14
87C196KT 87C196KS
BUS MODE 1 AC CHARACTERISTICS (Over Specified Operating Conditions) (Continued) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The system must meet these specifications to work with the 87C196KT Symbol TAVYV TLLYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 TOSC b 65 2 TOSC b 44 TOSC b 60 TOSC 0 Min Max 2 TOSC b 75 1 5 TOSC b 70 No Upper Limit TOSC b 30 2 TOSC b 75 1 5 TOSC b 60 Units ns ns ns ns(1) ns ns ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC c n where n e number of wait states If mode 0 (1 automatic wait state added) operation is selected add 2 TOSC to specification
15
15
87C196KT 87C196KS
MODE 1
87C196KT SYSTEM BUS TIMING
270999 - 23
16
16
87C196KT 87C196KS
BUS MODE 1
Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV
HOLD HOLDA TIMINGS (Over Specified Operation Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
Parameter HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid
b 25 b 25 b 15 b 10
Min
a 65 b 15 b 15
Max
Units ns(1)
a 15 a 15 a 25 a 25 a 15 a 15
ns ns ns ns ns ns ns ns
NOTE 1 To guarantee recognition at next clock
MODE 1
8XC196KT HOLD HOLDA TIMINGS
270999 - 11
17
17
87C196KT 87C196KS
BUS MODE 2 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 87C196KT will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCHLH TCLLL TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHIX TWHAX TRHBX TRHIX TRHAX Parameter Frequency on XTAL1 XTAL1 Period (1 FXTAL) XTAL1 High to CLKOUT High or Low CLKOUT Period CLKOUT High Period CLKOUT HIGH to ALE ADV High CLKOUT LOW to ALE ADV Low ALE ADV Cycle Time ALE ADV High Time Address Valid to ALE Low Address Hold After ALE ADV Low ALE ADV Low to RD Low RD Low to CLKOUT Low RD Low Period RD High to ALE ADV High RD Low to Address Float ALE ADV Low to WR Low CLKOUT Low to WR Low Data Valid before WR High CLKOUT High to WR High WR Low Period Data Hold after WR High WR High to ALE ADV High BHE Hold after WR High INST Hold after WR High AD8-15 Hold after WR High BHE Hold after RD High INST Hold after RD High AD8-15 Hold after RD High 0 5 TOSC b 10 TOSC b 22 2 TOSC b 25
b 10 a 15
Min 80 62 5
a 20
Max 16 0 125
a 85
Units MHz(1) ns ns ns
2 TOSC TOSC b 10 0 5 TOSC b 15 0 5 TOSC b 25 TOSC b 10 TOSC b 15 0 5 TOSC b 20 0 5 TOSC b 30 TOSC b 10 2 TOSC b 20 0 5 TOSC b 5 0 5 TOSC a 25
a5
TOSC a 27 0 5 TOSC a 20 0 5 TOSC a 15 TOSC a 10
ns ns ns ns(5) ns ns ns ns
4 TOSC
TOSC a 30
ns ns(5) ns(3) ns ns
TOSC a 25
ns ns ns ns(5) ns ns(3) ns ns(4) ns ns(4)
2 TOSC b 20 0 5 TOSC b 25 0 5 TOSC b 10 TOSC b 15 0 5 TOSC b 15 0 5 TOSC b 30 TOSC b 32 0 5 TOSC b 32 0 5 TOSC b 30 0 5 TOSC a 10
NOTES 1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz 2 Typical specifications not guaranteed 3 Assuming back-to-back bus cycles 4 8-bit bus only 5 If wait states are used add 2 TOSC c n where n e number of wait states
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87C196KT 87C196KS
BUS MODE 2 AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The system must meet these specifications to work with the 87C196KT Symbol TAVYV TLLYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX Parameter Address Valid to Ready Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD High 0 0 3 5 TOSC b 60 2 TOSC b 44 TOSC b 60 0 5 TOSC 0 Min Max 2 5 TOSC b 75 1 5 TOSC b 70 No Upper Limit TOSC b 30 2 5 TOSC b 75 1 5 TOSC b 60 Units ns ns ns ns(1) ns ns ns ns(2) ns(2) ns ns ns
NOTES 1 If Max is exceeded additional wait states will occur 2 If wait states are used add 2 TOSC c n where n e number of wait states If mode 0 (1 automatic wait state added) operation is selected add 2 TOSC to specification
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87C196KT 87C196KS
MODE 2
87C196KT SYSTEM BUS TIMING
270999 - 12
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20
87C196KT 87C196KS
MODE 2
87C196KT READY TIMINGS (ONE WAIT STATE)
270999 - 13
MODE 2
87C196KT BUSWIDTH TIMINGS
270999 - 14
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87C196KT 87C196KS
BUS MODE 2
Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV
HOLD HOLDA TIMINGS (Over Specified Operation Conditions) Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
Parameter HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float HLDA Low to BHE INST RD WR Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid
b 25 b 25 b 15 b 10
Min
a 65 b 15 b 15
Max
Units ns(1)
a 15 a 15 a 25 a 25 a 15 a 15
ns ns ns ns ns ns ns ns
NOTE 1 To guarantee recognition at next clock
MODE 2
8XC196KT HOLD HOLDA TIMINGS
270999 - 15
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87C196KT 87C196KS
AC CHARACTERISTICS
SLAVE PORT WAVEFORM
SLAVE PORT
(SLPL e 0)
270999 - 8
SLAVE PORT TIMING Symbol TSAVWL TSRHAV TSRLRH TSWLWH TSRLDV TSDVWH TSWHQX TSRHDZ
(SLPL e 0 1 2 3) Parameter Address Valid to WR Low RD High to Address Valid RD Low Period WR Low Period RD Low to Output Data Valid Input Data Setup to WR High WR High to Data Invalid RD High to Data Float 20 30 15 Min 50 60 TOSC TOSC 60 Max Units ns ns ns ns ns ns ns ns
NOTES 1 Test Conditions FOSC e 16 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change
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87C196KT 87C196KS
AC CHARACTERISTICS
SLAVE PORT WAVEFORM
SLAVE PORT (Continued)
(SLPL e 1)
270999 - 9
SLAVE PORT TIMING Symbol TSELLL TSRHEH TSLLRL TSRLRH TSWLWH TSAVLL TSLLAX TSRLDV TSDVWH TSWHQX TSRHDZ
(SLPL e 1 2 3) Parameter CS Low to ALE Low RD or WR High to CS High ALE Low to RD Low RD Low Period WR Low Period Address Valid to ALE Low ALE Low to Address Invalid RD Low to Output Data Valid Input Data Setup to WRHigh WR High to Data Invalid RD High to Data Float 20 30 15 Min 20 60 TOSC TOSC TOSC 20 20 60 Max Units ns ns ns ns ns ns ns ns ns ns ns
NOTES 1 Test Conditions FOSC e 16 MHz TOSC e 60 ns Rise Fall Time e 10 ns Capacitive Pin Load e 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change
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87C196KT 87C196KS
EXTERNAL CLOCK DRIVE
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 4 62 5 0 35 c TOSC 0 35 c TOSC Max 16 250 0 65 TOSC 0 65 TOSC 10 10 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270999 - 16
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270999 - 18 270999 - 17
AC Testing inputs are driven at 3 5V for a logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 2 0V for a logic ``1'' and 0 8V for logic ``0''
For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH VOL level occurs IOL IOH s 15 mA
THERMAL CHARACTERISTICS Device and Package AN87C196KT KS (68-Lead PLCC) iJA 36 5 C W iJC 13 C W
EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions H High L Low V Valid X No Longer Valid Z Floating Signals A Address B BHE BR BREQ C CLKOUT D DATA G Buswidth H HOLD HA HLDA L ALE ADV Q Data Out RD RD W WR WRH WRI X XTAL1 Y READY
NOTES 1 iJA e Thermal resistance between junction and the surrounding environmental (ambient) Measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package surface (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typical variations are g2 C W 3 Values listed are at a maximum power dissipation of 0 50W
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87C196KT 87C196KS
EPROM SPECIFICATIONS
AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions Load Capacitance e 150 pF TC e 25 C g5 C VCC VREF e 5 0V g0 5V VSS ANGND e 0V VPP e 12 5V g0 25V EA e 12 5V g 0 25V Fosc e 5 0 MHz Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TLHPL TPHLL TPHDX TPHPL TLHPL TPLDV TSHLL TPHIL TILIH TILVH TILPL TPHVL Paramter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE Pulse Width PROG Pulse Width(2) PALE High to PROG Low PROG High to next PALE Low Word Dump Hold Time PROG High to next PROG Low PALE High to PROG Low PROG Low to Word Dump Valid RESET High to First PALE Low PROG High to AINC Low AINC Pulse Width PVER Hold after AINC Low AINC Low to PROG Low PROG High to PVER Valid 1100 0 240 50 170 220 220 220 50 Min 0 100 0 400 50 50 220 220 50 Max Units TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC TOSC
NOTES 1 Run-time programming is done with Fosc e 6 0 MHz to 10 0 MHz VCC VPD VREF e 5V g0 5V TC e 25 C g5 C and VPP e 12 5V g0 25V For run-time programming over a full operating range contact factory 2 Programming specifications are not tested but guaranteed by design 3 This specification is for the word dump mode For programming pulses use 300 Tosc a 100 ms
DC EPROM PROGRAMMING CHARACTERISTICS Symbol IPP Parameter VPP Programming Supply Current Min Max 200 Units mA
NOTE VPP must be within 1V of VCC while VCC k 4 5V VPP must not have a low impedance path to ground or VSS while VCC l 4 5V
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87C196KT 87C196KS
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270999 - 19
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
270999 - 20
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87C196KT 87C196KS
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT
270999 - 21
AC CHARACTERISTICS
SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING SHIFTING REGISTER MODE Test Conditions TA e b 40 C to a 125 C VCC e 5 0V g10% VSS e 0 0V Load Capacitance e pF Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX(8) TXHQZ(8) Parameter Serial Port Clock Period Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float 2 TOSC a 200 0 5 TOSC Min 8 TOSC 4 TOSC b 50 3 TOSC 2 TOSC b 50 2 TOSC a 50 TOSC a 50 Max Units ns ns ns ns ns ns ns ns
NOTE 8 Parameters not tested
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87C196KT 87C196KS
WAVEFORM
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT WAVEFORM
SHIFT REGISTER MODE
270999 - 22
A TO D CHARACTERISTICS
The sample and conversion time of the A D converter in the 8-bit or 10-bit modes is programmed by loading a byte into the AD TIME Special Function Register This allows optimizing the A D operation for specific applications The AD TIME register is functional for all possible values but the accuracy of the A D converter is only guaranteed for the times specified in the operating conditions table The value loaded into AD TIME bits 5 6 7 determines the sample time SAMP The value loaded into AD TIME bits 0 1 2 3 and 4 determines the bit conversion time CONV These bits as well as the equation for calculating the total conversion time T are shown in the following table AD TIME
7 6 Sample Time (SAMP) 4n a 1 state times n e 1 to 7 5 4
The converter is ratiometric so absolute accuracy is dependent on the accuracy and stability of VREF VREF must be close to VCC since it supplies both the resistor ladder and the analog portion of the converter and input port pins There is also an AD TEST SFR that allows for conversion on ANGND and VREF as well as adjusting the zero offset The absolute error listed is without doing any adjustments A D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet Testing is performed with VREF e 5 12V and 16 MHz operating frequency After a conversion is started the device is placed in IDLE mode until the conversion is complete
1FAFH Byte
3 2 1 0 Bit Conversion Time (CONV) n a 1 state times n e 2 to 31
Equation T e (SAMP) a Bx (CONV) a 2 5 T e total conversion time (states) B e number of bits conversion (8 or 10) n e programmed register value
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87C196KT 87C196KS
10-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min
b 40
Max
a 125
Units C V V(1) ms(2) ms(2) MHz
4 50 4 50 20 15 40
5 50 5 50
18 16 0
NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications
10-BIT MODE A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Sampling Capacitor
g1 0 g0 1 g0 25
(Using Above Operating Conditions)(6) Min 1024 10 0 Max 1024 10
g3 0
Typ (1)
Units Level Bits LSBs LSBs LSBs
0 25 g0 5 0 25 g0 5 1 0 g2 0
b 0 75
g3 0
LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1)
a 0 75
g1 0
0 0
0 009 0 009 0 009
b 60 b 60 b 60
dB(1 2 3) dB(1 2) dB(1 2) X(4) mA pF
750 0
1 2K
g1 5
30
An ``LSB'' as used here has a value of approximately 5 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 All conversions performed with processor in IDLE mode
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87C196KT 87C196KS
8-BIT MODE A D OPERATING CONDITIONS
Symbol TA VCC VREF TSAM TCONV FOSC Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min
b 40
Max
a 125
Units C V V(1) ms(2) ms(2) MHz
4 50 4 50 20 12 40
5 50 5 50
15 16 0
NOTES 1 VREF must be within 0 5V of VCC 2 The value of AD TIME is selected to meet these specifications
8-BIT MODE A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 30
g1 0 g0 25 g0 5 g0 5
(Using Above Operating Conditions)(6) Min 256 8 0 Max 256 8
g1 0
Typ (1)
Units Level Bits LSBs LSBs LSBs
0
b0 5
g1 0
LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1)
a0 5
g1 0
0 0
0 003 0 003 0 003
b 60 b 60 b 60
dB(1 2 3) dB(1 2) dB(1 2) X(4) mA V(5) pF
750 0 ANGND b 0 5
1 2K
g1 5
VREF a 0 5
An ``LSB'' as used here has a value of approximately 20 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break-before-make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltage beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode
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87C196KT 87C196KS
7 REGISTER RAM OVERWRITE (A-step B-step) If a write is performed to a byte word location within the SFR range of 1F60h to 1FFFh the data to be written is also written to a correspondding location located within the REGISTER RAM space 360h to 3FFh To determine the address of the REGISTER RAM location that is overwritten an offset of 1C00h can be subtracted from the byte word addressed in the SFR range 8 BUS TIMING MODES 1 AND 2 (A-step B-step) Bus timing modes 1 and 2 are not featured or specified on A-step and B-step parts On C-step parts Mode 1 is selected by setting bits MSEL1 e 0 and MSEL0 e 1 in the CCB1 register Mode 2 is similarly selected by setting MSEL1 e 1 and MSEL0 e 0 Timings are altered by Mode 1 and Mode 2 as follows (for actual values see the Bus Mode 1 and Bus Mode 2 AC Characteristics in this data sheet) Mode 1 RD WR advanced 1 TOSC ALE advanced 0 5 TOSC ALE pulse width remains 1 TOSC Mode 2 RD WR advanced 1 TOSC ALE advanced 0 5 TOSC ALE pulse width remains 1 TOSC Address advanced 0 5 TOSC 9 VOH2 (A-step b-step) A- and B-step parts are capable of VOH2 e VCC b 1V with IOH e b 6 mA C-step devices meet the target values of VOH2 e VCC b 1V with IOH e b 15 mA 10 CLKOUT DURING RESET (A-step B-step C-step) For all steppings of the 87C196KT the CLKOUT function during RESET (P2 7) differs from the 87C196KR C-step During RESET on the 87C196KT CLKOUT does not toggle and remains in the high state During RESET on the 87C196KR C-step CLKOUT countinues to toggle
87C196KT KS ERRATA
The following is a list of all known functional deviations for 87C196KT KS devices B-step and later devices can be identified by a special mark following the eight digit FPO number on the top of the package For C-step devices this mark is a ``C'' 1 HOLD OR READY DURING DIVIDE (A-step) There is a bug in the DIV and DIVB (signed divide) instructions such that if the following 2 conditions are met there may be an error of 1 in the quotient a) HOLD or READY is asserted during the first state of execution of the DIV and DIVB instruction b) HOLD or READY duration is 16 state times for the DIVB or 24 state times for a DIV instruction 2 P2 7 (CLKOUT) (A-step) Port 2 7 (CLKOUT) does not operate in open drain mode 3 P2 REG 7 AND P6 REG 4 THROUGH P6 REG 7 CLEARED (A-step) P2 REG 7 is cleared when P2 SSEL 7 bit is changed from a 1 to a 0 (special function to LSIO) P6 Reg 4- 7 is cleared when the corresponding P6 SSEL 4- 7 is changed from a 1 to a0 4 INDIRECT SHIFT INSTRUCTION (A-step) The upper three bits of the byte register holding the shift count are not masked completely If the shift count register has the value 32 x n where n e 1 3 5 or 7 the operand wil be shifted 32 times The above condition results in NO shift taking place 5 INTERNAL RAM POWERDOWN LEAKAGE (A-step) If an invalid address is applied to the internal RAM during power-down the address lines float This can cause increased current consumption during power-down To insure a valid address on the internal RAM execute the idle power-down instruction from internal RAM 6 INST PIN (A-step) On A-step devices the INST pin is pulled medium low for approx 200 ns after RESET and then pulled weakly HIGH until P5SSEL is written to This is corrected on B-step devices where the INST pin is pulled medium low for approx 200 ns after RESET and is then pulled weakly LOW until P5SSEL is written to
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87C196KT 87C196KS
87C196KT KS DESIGN CONSIDERATIONS
1 EPA TIMER RESET WRITE CONFLICT If the user writes to the EPA timer at the same time that the timer is reset it is indeterminate which will take precedence Users should not write to a timer if using EPA signals to reset it 2 VALID TIME MATCHES The timer must increment decrement to the compare value for a match to occur A match does not occur if the timer is loaded with a value equal to an EPA compare value Matches also do not occur if a timer is reset and 0 is the EPA compare value 3 P6 PIN 4- 7 NOT UPDATED IMMEDIATELY Values written to P6 REG are temporarily held in a buffer If P6 MODE is cleared the buffer is loaded into P6 REG x If P6 MODE is set the value stays in the buffer and is loaded into P6 REG x when P6 MODE x is cleared Since reading P6 REG returns the current value in P6 REG and not the buffer changes to P6 REG cannot be read until unless P6 MODE x is cleared 4 WRITE CYCLE DURING RESET If RESET occurs during a write cycle the contents of the external memory device may be corrupted 5 INDIRECT SHIFT INSTRUCTION The upper 3 bits of the byte register holding the shift count are not masked completely If the shift count register has the value 32 c n where n e 1 3 5 or 7 the operand will be shifted 32 times This should have resulted in no shift taking place 6 PORT 4 ADDRESS BEHAVIOR For bus timing Modes 1 and 2 specified only on the 87C196KT KS C-step Port 4 does not retain the address during the data portion of the bus cycle Designs using an 8-bit external memory system in bus Mode 1 or Mode 2 require an external latch on Port 4 to retain the address during the data portion of the bus cycle Designs using an 8-bit external memory system in the KR or KR a 1 Wait bus timing modes do not require an external latch Designs using 16-bit external memory systems require an external latch on both Port 3 and Port 4 in all bus timing modes
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87C196KT 87C196KS
DATA SHEET REVISION HISTORY
This is the -007 revision of the 8XC196KT KS Data Sheet The following differences exist between the -006 revision and the -007 revision 1 VOL3 estimate added 2 ``Voltage on Analog Input Pin'' removed Parameter covered by Note 1 VREF must be within 0 5V of VCC 3 The Data Sheet Revision History was updated to reflect changes made for this version of the datasheet (-007)
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